1 ;THE COMPUTER CODE CONTAINED HEREIN IS THE SOLE PROPERTY OF PARALLAX
2 ;SOFTWARE CORPORATION ("PARALLAX"). PARALLAX, IN DISTRIBUTING THE CODE TO
3 ;END-USERS, AND SUBJECT TO ALL OF THE TERMS AND CONDITIONS HEREIN, GRANTS A
4 ;ROYALTY-FREE, PERPETUAL LICENSE TO SUCH END-USERS FOR USE BY SUCH END-USERS
5 ;IN USING, DISPLAYING, AND CREATING DERIVATIVE WORKS THEREOF, SO LONG AS
6 ;SUCH USE, DISPLAY OR CREATION IS FOR NON-COMMERCIAL, ROYALTY OR REVENUE
7 ;FREE PURPOSES. IN NO EVENT SHALL THE END-USER USE THE COMPUTER CODE
8 ;CONTAINED HEREIN FOR REVENUE-BEARING PURPOSES. THE END-USER UNDERSTANDS
9 ;AND AGREES TO THE TERMS HEREIN AND ACCEPTS THE SAME BY USE OF THIS FILE.
10 ;COPYRIGHT 1993-1998 PARALLAX SOFTWARE CORPORATION. ALL RIGHTS RESERVED.
12 ; $Source: /cvs/cvsroot/d2x/arch/dos_vgaregs.inc,v $
15 ; $Date: 2001-01-29 13:35:08 $
17 ; Readable descriptions of VGA ports.
19 ; $Log: not supported by cvs2svn $
20 ; Revision 1.1.1.1 2001/01/19 03:30:15 bradleyb
23 ; Revision 1.1.1.1 1999/06/14 21:58:45 donut
24 ; Import of d1x 1.37 source.
26 ; Revision 1.2 1993/10/15 16:22:45 john
27 ; *** empty log message ***
29 ; Revision 1.1 1993/09/08 11:41:00 john
36 %define MISC_OUTPUT 03c2h ;Miscellaneous Output register
37 %define MAP_MASK 02h ;index in SC of Map Mask register
38 %define READ_MAP 04h ;index in GC of the Read Map register
39 %define BIT_MASK 08h ;index in GC of Bit Mask register
41 %define SC_INDEX 3c4h ;Index register for sequencer ctrl.
42 %define SC_MAP_MASK 2 ;Number of map mask register
44 %define SC_INDEX 3c4h ;Index register for sequencer ctrl.
45 %define SC_MAP_MASK 2 ;Number of map mask register
46 %define SC_MEM_MODE 4 ;Number of memory mode register
48 %define GC_INDEX 3ceh ;Index register for graphics ctrl.
49 %define GC_READ_MAP 4 ;Number of read map register
50 %define GC_GRAPH_MODE 5 ;Number of graphics mode register
51 %define GC_MISCELL 6 ;Number of miscellaneous register
53 %define CRTC_INDEX 3d4h ;Index register for CRT controller
54 %define CC_MAX_SCAN 9 ;Number of maximum scan line reg.
55 %define CC_START_HI 0Ch ;Number of start address high register
56 %define CC_START_LO 0Dh ;Number of start address low register
57 %define CC_UNDERLINE 14h ;Number of underline register
58 %define CC_MODE_CTRL 17h ;Number of mode control register
59 %define CRTC_OFFSET 13h ; CRTC offset register index
61 %define DAC_WRITE_ADR 3C8h ;DAC write address
62 %define DAC_READ_ADR 3C7h ;DAC read address
63 %define DAC_DATA 3C9h ;DAC data register
65 %define VERT_RESCAN 3DAh ;Input status register #1